1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a gate dielectric layer.
2. Description of the Related Art
With the rapid development of the integrated circuit fabrication technologies, the production of highly efficient, highly integrated, low cost, light and compact electronic devices has become the design goal for many types of electronic products. At present, most semiconductor manufacturers need to fabricate devices with a variety of functions on the same chip in order to attain the above target.
Integrating both high voltage devices and low voltage devices together on the same chip is one of the methods that meet the above requirements. For example, low voltage devices can be used for fabricating control circuit and high voltage devices can be used for fabricating electrically programmable read-only-memory (EPROM), flash memory or the driving circuit of liquid crystal display.
However, in order to take a higher breakdown voltage, the thickness of the gate oxide layer in the high voltage devices frequently has to be greater than 200 Å, which is considerably greater than the thickness of the gate oxide layer in the low voltage devices. With this particular requirement, many problems emerge in the process of integrating the high voltage devices with the low voltage devices.
FIGS. 1A through 1F are schematic cross-sectional views showing the process of fabricating a conventional gate oxide layer. First, as shown in FIG. 1A, a pad oxide layer 110 and a mask layer 120 are formed on a high voltage circuit region 101 and a low voltage circuit region 102 of a common substrate 100. Thereafter, the pad oxide layer 110 and the mask layer 120 are patterned.
As shown in FIG. 1B, using the mask layer 120 as a mask, the substrate 100 is etched to from a trench 130. Thereafter, a silicon oxide layer 140 is formed over the substrate 100 to fill the trench 130 completely and cover the substrate 100. After that, the silicon oxide layer 140 is removed until the mask layer 120 is exposed and an active region 145 is simultaneously defined.
As shown in FIG. 1C, a wet etching operation is carried out to remove the mask layer 120 and the pad oxide layer 110. In the process of removing the mask layer 120 and the pad oxide layer 110 in the wet etching operation, the etching solution will erode parts of the silicon oxide layer to form divots 150 at the side corner regions of the trench 130.
As shown in FIG. 1D, a thick high voltage gate oxide layer 160 is formed over the substrate 100. Due to the presence of divots 150, the rate of oxidation in the process of forming the gate oxide layer 160 will be affected around the corner regions of the shallow trench isolation structures close to the divots. Therefore, the high-voltage gate oxide layer 160 around the corner regions of the shallow trench isolation structures will have a thickness smaller than the high-voltage gate oxide layer 160 in the active region 145. Such non-uniformity in the thickness of the gate oxide layer is the so-called ‘gate oxide thinning’ phenomenon. This phenomenon often leads to electrical problems in the device and an undesirable drop in the reliability of the gate oxide layer.
As shown in FIG. 1E, a photoresist layer 165 is formed to cover the high-voltage circuit region 102. Then, using the photoresist layer 165 as a mask, the high-voltage gate oxide layer 160 in the low-voltage circuit region 102 is removed. In the process of removing the high-voltage gate oxide layer to from the low-voltage circuit region 102, the silicon oxide 140 will also be etched because the silicon oxide layer 140 and the high-voltage gate oxide layer 160 are fabricated using the same oxide material. Hence, the shallow trench isolation structures (the silicon oxide layer 140) in the low-voltage circuit region 102 will have a depression 168.
As shown in FIG. 1F, the photoresist layer 165 is removed and then a thin low-voltage gate oxide layer 170 is formed over the substrate 100 by performing an oxidation process. Then, a doped polysilicon layer 180 is formed over the substrate. After forming the doped polysilicon layer 180, a parasitic transistor is produced near the divots 150 at the corner regions of the shallow trench isolation structures in the high-voltage circuit region 101. During a normal memory operation, these parasitic transistors may produce current leaks. In other words, the divots 150 may accumulate electric charges and generate sub-threshold current in the integrated circuit leading to the so-called kink effect. The kink effect not only will lead to a drop in the quality of the device and a lowering of the stability and reliability of the device, but also will lead to a reduction in the process yield. On the other hand, because of the presence of a depression 168 in the low-voltage circuit region 102, doped polysilicon will fill the depression 168 area leading to junction leakage problems. Hence, not only is the power consumption increased, but the operating time of the device is also lengthened.